The present invention relates to a reference potential generating circuit and a semiconductor integrated circuit arrangement or the like using the same.
Inside of a dynamic random access memory (DRAM) as an example of a semiconductor memory, there are required, in order to assure reliability and a decrease in electric current consumed therein, a variety of voltage levels such as an internal dropped voltage level Vint, a word line increased voltage level VPP, a bit line precharge level Vpr, a substrate bias level VBB and the like, in addition to an externally supplied power voltage level VCC. In a 16M-bit DRAM in which, for example, the VCC is equal to 5 V (with the earth potential VSS=0 V serving as a reference), Vint=3.3 V, VPP=4.5 V, Vpr=1.65 V and VBB=-2 V are generally used.
To obtain such voltage levels, there has been conventionally used a power supply voltage converting circuit using MOSFETs (field-effect-type MOS transistors) as disclosed in Japanese Patent Laid-Open Publication No. 63-244217. However, such a power supply voltage converting circuit presents the problem that, even though variations of an output voltage thereof due to variations of the external power supply voltage level VCC can be restrained, the output voltage varies if the threshold voltages of the MOSFETs vary due to variations of the temperature thereof.
In a semiconductor integrated circuit such as a DRAM or the like, when synchronously operating a plurality of circuit blocks, there are used a variety of delay circuits for adjusting the input/output timings in these circuit blocks. This will be more specifically discussed in the following with a DRAM taken as an examle. In the peripheral circuit block for example, there are disposed a row decoder for selecting memory cells through a word line, and a timing circuit for adjusting the timing at which the sensing amplifier is so activated as to amplify a small potential read out, to a bit line concerned, from one of the memory cells selected by the row decoder. The timing circuit causes activation of the sensing amplifier to be delayed with respect to the selection of a word line by the row decoder. The timing circuit can be formed by a normal inverter chain having a plurality of inverter stages, each inverter comprising two MOSFETs only. In the timing circuit having such a simple arrangement, the delay time therein presents a great temperature dependency.
To reduce the delay time in temperature dependency, there has been proposed a CR delay circuit utilizing time constant to be determined by a resistance element and a capacitor element. Examples of such a CR delay circuit include a CR delay circuit discussed in Japanese Patent Laid-Open Publication No. 63-312715, and a CR delay circuit discussed in "A New CR-Delay Circuit Technology for High-Density and High-Speed DRAMs", IEEE J. Solid-State Circuits, vol. 24, pp. 905-910, 1989 by Yohji WATANABE et al.
FIG. 40 shows an example of a semiconductor integrated circuit arrangement using conventional CR delay circuits. In the semiconductor integrated circuit arrangement in FIG. 40, a peripheral circuit block 302 has a plurality of stages of CR delay circuits 301. Each of the CR delay circuits 301 comprises a comparator circuit 303, a P-type MOSFET 304, an N-type MOSFET 305, an input signal P1, an output signal P2, a charging resistance element R1, voltage-dividing resistance elements R2, R3, and a capacitor element C. From a constant voltage generating circuit 306, a voltage VCC obtained by stabilizing an externally supplied power voltage, is supplied, as an internal power supply voltage, to each of the CR delay circuits 301.
According to the arrangement above-mentioned, the delay time in each of the CR delay circuits 301 depends only constants to be determined by the geometrical dimensions of the resistance elements R1 to R3 and of the capacitor element C. This reduces the delay time in temperature dependency. However, in a semiconductor integrated circuit arrangement, when the conventional CR delay circuits 301 are used in the peripheral circuit block at all parts thereof in which it is required to delay the output signals, the peripheral circuit block is disadvantageously increased in layout area as compared with an arrangement using delay circuits formed by normal inverter chains.